Consumers continue to demand higher performance and lower cost electronic products incorporating an increasing number of features. These market demands have resulted in increased miniaturization of components and greater packaging density of integrated circuits (“IC's”). The increasing functionality and decreasing size and number of system components make IC's increasingly susceptible to damage during manufacturing and in use. Integrated circuit packages are commonly used to encase the IC and provides protection and electrical connectivity to external circuitry and components.
IC devices—also known as semiconductor dies—are constructed from a silicon or gallium arsenide wafer through a process that comprises a number of deposition, masking, diffusion, etching, and implanting steps. Usually, many individual devices are constructed on the same wafer. When the devices are separated into individual rectangular units, each takes the form of an IC die. In order to interface a die with other circuitry, it is common to mount it on a leadframe or on a multi-chip module base leadframe that is surrounded by a number of lead fingers. Each die has bonding pads that are then individually connected in a wire-bonding operation to the leadframe's lead finger pads using extremely fine gold or aluminum wires. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies.
IC packaging technology has shown an increase in semiconductor chip density (the number of chips mounted on a single circuit board or base leadframe) that parallels the reduction in the number of components that are needed for a circuit. This results in packaging designs that are more compact, in form factors (the physical size and shape of a device) that are more compact, and in a significant increase in overall IC density. However, IC density continues to be limited by the space (or “real estate”) available for mounting individual die on a base leadframe.
To condense further the packaging of individual devices, packages have been developed in which more than one device can be packaged at one time at each package site. Each package site is a structure that provides mechanical support for the individual IC devices. It also provides one or more layers of interconnect lines that enable the devices to be connected electrically to surrounding circuitry. Of importance to complicated packaging designs are considerations of input/output count, heat dissipation, matching of thermal expansion between a motherboard and its attached components, cost of manufacturing, ease of integration into an automated manufacturing facility, package reliability, and easy adaptability of the package to additional packaging interfaces such as a printed circuit board (“PCB”).
In some cases, multi-chip devices can be fabricated faster and more cheaply than a corresponding single IC chip, that incorporates all the same functions. Current multi-chip modules typically consist of a PCB base package substrate onto which a set of separate IC chip components is directly attached. Such multi-chip modules have been found to increase circuit density and miniaturization, improve signal propagation speed, reduce overall device size and weight, improve performance, and lower costs—all primary goals of the computer industry.
However, such multi-chip modules can be bulky. IC package density is determined by the area required to mount a die or module on a circuit board. One method for reducing the board size of multi-chip modules and thereby increase their effective density is to stack the die or chips vertically within the module or package.
Such designs are improvements over prior multi-chip package and system-in-a-package (“SiP”) designs that combined several semiconductor die and associated passive components (“passives”) side by side in a single, horizontal layer. Combining them into a single horizontal layer used board space inefficiently by consuming large base package substrate areas, and afforded less advantage in circuit miniaturization.
However, multi-chip modules, whether vertically or horizontally arranged, can also present problems because they usually must be assembled before the component chips and chip connections can be tested. That is, because the electrical bond pads on a die are so small, it is difficult to test die before assembly onto a base package substrate. Thus, when die are mounted and connected individually, the die and connections can be tested individually, and only known-good-die (“KGD”) free of defects are then assembled into larger circuits. A fabrication process that uses KGD is therefore more reliable and less prone to assembly defects introduced due to bad die. With conventional multi-chip modules, however, the die cannot be individually identified as KGD before final assembly, leading to KGD inefficiencies and assembly process problems including yield.
An Internal Stacking Module (ISM) is a package component that includes a packaged IC circuit and that can be assembled into a larger multi-chip package. Internal stacking modules can be pre-tested prior to assembly into a larger package, and therefore can be sorted as Known Good Packages (KGP) prior to assembly into a larger multi-chip package.
Semiconductor dies containing integrated circuits need to be protected from external sources of electromagnetic radiation that may impact circuit operation. To prevent electromagnetic interference, groups of packaged semiconductor devices may be placed in a module or box. The module shields the semiconductor devices from electromagnetic interference (EMI). Even though a shielded module may provide overall EMI protection from outside interference, semiconductor devices inside the module can still interfere with each other.
Given the increased functionality of new electronic products such as advanced cell phones, there is a need for semiconductor packages that include features for shielding semiconductor dies from electromagnetic interference. Such functionality enables placing EMI-sensitive components in the proximity of sources of electromagnetic radiation.
The main issues with existing shielding approaches are the lack of lateral shielding of the semiconductor die and lack of an effective and reliable approach for connecting the shield to a ground loop using the least number of lead connections.
Despite the advantages of recent developments in semiconductor fabrication and packaging techniques, there is a continuing need for improved packaging methods, systems, and designs for increasing semiconductor die density in PCB assemblies that include components with added electromagnetic interference shielding.
In view of the increasing requirements for multi-chip packages with effective EMI shielding, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.